1. Field of the invention
The present invention relates to a cache memory, and more specifically to a cache controller capable of giving a high versatility of cache memory structure.
2. Description of related art
Large computers, which have been called a "main frame", and a high rank of minicomputers comprise a cache memory as an indispensable element for the purpose of speeding up the access to a main memory. In these large and intermediate sizes of computers, the cache memories have been designed to be closely coupled to a central processor (CPU) so that an optimum cost performance is realized in relation to the CPU. In brief, a logic unit associated to the cache memory is made sufficiently integral with the CPU. Accordingly, the cache unit has a fixed cache memory structure and association unit number and is not made into the form of a module or discrete unit.
On the other hand, so-called personal computers and a small size of systems such as a "engineering work station" have a multi-chip hardware logic which is composed of standard integrated circuits. For example, most of the hardware logic includes several boards to ten and several boards.
At present, the above small scaled computers are required to have performance comparable to the main frame, and it has already become possible from a technical aspect. Accordingly, it is a matter of course that the small scaled computers need the cache memory. Today, there can already be found a single board computer having a cache memory composed of discrete integrated circuits to utilize the performance of the CPU to a maximum extent.
An important feature of the small size of computers lies upon an elaborated utilization of standard integrated circuits (LSIs) as well as versatility of system structure composed of standard parts. This makes it possible to achieve two objects apparently inconsistent to each other, namely, mass production of the system which is one important condition of domestic products, and multikind and small-quantity production for complying diversification in accordance with various requests of users.
In fact, even in the field of the small size of computers, the personal computer and the engineering work station are different in required performance, in the degree of specialization and generalization, and in permitted production cost. In other words, these computers have a different equilibrium point between cost and performance.
As a result, the cache memory used in the small size of computers has a different equilibrium point between cost and performance, in accordance with the type of computers. For example, the performance of the cache memory is determined by an average memory access time which is dependent upon a cache hit ratio, a cache access time and a miss hit ratio. The cache hit ratio is a function of a total size of cache, a block size of cache, the number of association units (associability; n-way), a fetch algorithm, etc. The cache access time is dependent upon a clock frequency for cache access operation, an output delay time for each element, an input setting time of each element, etc. Further, the miss hit ratio depends upon the amount of bus interface logic elements, a bus transfer speed, a bus availability ratio, etc. On the other hand, the manufacturing cost for cache memories is determined by a unit price of elements used, a total amount of logic elements used, a fixed expense, etc. The total amount of logic elements used is dependent upon a total size of cache, a block size of cache, the number of association units (associability; n-way), the amount of bus interface logic elements, etc.
As seen from the above, in order to elevate the performance of a cache memory, it is necessary to improve the cache access time, the cache hit ratio, and others. On the other hand, the manufacture cost depends directly upon the unit prices and the number of necessary parts. In addition, it would be a matter of course that improvement of performance by modifying hardware will result in increase of cost.
The factor dependent upon the cost is not limited to only the performance, but also reliability depends upon the cost. The reason for this is that an increase in redundancy of hardware will inevitably accompany the cost-up.
Accordingly, in order to realize a high performance cache memory, it is of course necessary to freely use an advanced integrated circuit technology to a maximum extent so as to manufacture high performance and multifunction parts. However, only the advanced integrated circuit cannot provide a cache memory which sufficiently satisfies both the cost and the performance, dependently upon various requests based on different applications. In general, the multikind and small-quantity production will result in an increase of cost.